• 作者： 陳正
• 作者服務機構： 國立交通大學計算機科學系
• 中文摘要： 本文之主要目的在研究以一套規則之演繹法(Algorithms)完成數位系統中異步時序邏輯線路之設計工作。在傳統之異步邏輯線路設計上分成四個階段:第一階段為將線路之要求與敘述((Verbal descriptions)建立原始流程表(Primitive flow table)，此步驟為分析之工作。第二階段是將原始流程表給予最簡化(Minimization)，在本篇中介紹以三個演繹法完成之。第三階段是將最簡化之流程表給予最佳之狀態分配(Optimum state assignment)。本篇依據Tracey之理論及觀念，以四個演繹法分別產生K-set partitionlist，化簡為布氏矩陣(Boolean matrix)及求得最後之狀態分配。最後階段，利用組合邏輯線路之演繹法將線路合成。本篇內介紹之演繹法最大特點，是將異步時序邏輯線路之設計給予系統化與規則化，易於由計算機處理，在研究教學上可提供為參考。
• 英文摘要： In this paper, the algorithmetic synthesis of asynchronous sequential logic CKT are studied and introduced. There are four steps in the design of asynchronous sequential logic: the first step is to construct the primitive flow table from the original verbal description, the second step is to minimize the flow tables, the third step is to obtain the optimum state assignment and the last step is the implementation of the final CKT. We assume that the primitive flow table is obtained initially. We have developed three algorithms to generate the set of all compatible pairs, maximal compatibles and minimum or nearly minimal closed covers. The first two algorithms are straightforward and the third algorithm is quite involved. As for the state assignment, first we give a k-set partition list generator to generate all k-set partitions. Then we form the Boolean matrix and reduce it by using matrix reduction algorithm. The reduced matrix is the content of state assignment with minimum state transition and critical race-free. After the states have been assigned, we can form an F-array from the assigned flow table, and then derive the minimum form of each excitation variable and output variable by using extraction algorithm developed in the design of combinational logic CKT.
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