- 作者: 李舉賢
- 作者服務機構: Electrical Engineering Department National Taiwan University
- 中文摘要: The basic single-stage storage transistor delay circuits are cascaded to constructa multi-stage delay circuit and its performances are studied. In a two-stage cas-caded delay circuit a delay time ranging from 2 usec to 3 usec was obtained.
- 英文摘要: --
- 中文關鍵字: --
- 英文關鍵字: --