- 作者: 賴飛龍;吳全祐;趙振良;龐台銘
- 作者服務機構: 國立臺灣大學電機及資訊工程學系
- 中文摘要: 對於大型的快取記憶體而言,?擬位址的轉換和快取記憶體的存取之關係會影響到整個機器的執行速度。使用實際位址去存取的快取記憶體會因?位址的轉?而拉長存取時間,使用?擬位址存取的快取記憶體有較快的速度, 可是同義問題確是很難去解決。經由對於軟體的加以限制及一些硬體的支援,我們的?擬定址實際標記的快取記憶 體能夠和傳統的?擬快取記憶體有同樣的存取速度,並且解?同義問題。將快取記憶體是否取得所要資料的訊號加以延後通知中央處理單元,使得TLB的存取得以不降低快取記憶體的速度。在這顆晶片上只需要一些硬體就能簡單 的解決TLB同值問題。
- 英文摘要: For large caches, the interaction between cache access and address translation affects the machine cycle time and the access time to memory. Physically addressed caches slow down cache access due to virtual address translation. Virtually addressed caches are faster, but the accompanying synonym problem is difficult to handle. With some software constraints and hardware support, our virtually addressed physically tagged caches can achieve the same speed as traditional virtually addressed caches and solve the synonym problem. The design of the delayed miss signal excludes TLB access from the critical path of the cache access. A simple method to solve the TLB coherence is implemented in this chip and only a small amount of hardware is required.
- 中文關鍵字: cache coherency; coherency protocol; delayed miss; snooping cache; synonym problem; write back; write buffer; write through
- 英文關鍵字: --