• 作者： 李毅郎; 賴盈照; 吳誠文
• 作者服務機構： 國立清華大學電機工程學系
• 中文摘要： 隨著超大型積體電路技術不斷的進步與硬體價格的降低，特殊用途機器由於具有平行處理的能力，越來越廣泛地被用在加速偵錯模擬上。在我們以前提出的二維細胞式自動機（CA）模型中，CA被當作單一指令流多重資料流（SIMD）的平行架構來加速邏輯與偵錯模擬。 在本論文中，我們提出一細胞式自動機晶片來實體化先前我們所提出的CA模型，此CA晶片具有快速平行處理邏輯與偵錯模擬的能力。由於使用導管式技術(pipeline)，我們的模擬機器在機器字組長度為8位元與時鐘頻率為20MHz的情況下，可以達到每秒模擬十億個邏輯閘的模擬速度。CA架構可以很簡單的往四個方向（上、下、左、右）擴充，也就是每個CA晶片能夠直接地與它四個相鄰的CA晶片互相溝通連接而形成一個較大的細胞式陣列。CA晶片有兩種工作模式：初使化模式與模擬模式；在模擬工作模式下，CA晶片能執行邏輯與偵錯模擬。當導管被填滿之後，每隔6個時鐘週期即會產生一組結果。和先前已發表的平行偵錯模擬器比較，我們的結果大約快了1000倍。
• 英文摘要： With advances in VLSI technology and the decline in hardware costs, special-purpose machineshave become more and more popular for a wide range of applications. We have proposed a unilateral2-D cellular automata (CA) model which can be treated as an SIMD parallel architecture. In this paper,we present a CA chip which realizes our previously proposed CA model for highly parallel logic and faultsimulation. By using pipelining, our CA simulation engine achieves a simulation rate of more than onebillion gate evaluations per second using a 20 MHz clock and 8-bit words. The CA architecture allowseasy scaling; i.e., each CA chip can directly communicate with its four neighboring CA chips to constructa larger cellular array. Our CA chip operates in either initialization or simulation mode and can performlogic and fault simulation. It produces one output in every six clock cycles after the pipeline has beenfilled. Compared with previously reported parallel fault simulators, its performance is superior by aboutthree orders of magnitude.
• 中文關鍵字： cellular automata; fault simulation; graph embedding; layered network; logic simulation; SIMD
• 英文關鍵字： --