- 作者: 陳茂傑
- 作者服務機構: 國立交通大學電子工程系
- 中文摘要: 本文對存在於矽磊晶層之電動性缺陷的特性進行觀察與分析。矽磊晶層是以加氫還元四氯化矽法在1050℃之溫度堆積於矽晶片上。磊晶堆積之前,該等矽晶片先經過高溫氧化熱處理,用以模擬製造電子元件的一般程序。矽磊晶經過萊特蝕刻(Wright Etch)而顯現出磊晶層堆積缺陷(Epitaxial Stacking Fault,簡稱SFepi)及小丘缺陷(Hillock)。應用陽極蝕刻法 (Anodic Etch)可以發現這兩種缺陷都屬於電動性缺陷,其中SFepi的電動性比Hillock的要來得活躍。如將矽磊晶片施以高溫濕氧熱處理,則原來的一部份Hillock可轉變成一種表面型氧化誘導堆積缺陷(Oxidation induced Stacking Faults)。砷離子佈植之掩埋層具有避免形成磊晶層堆積缺陷之效用。另一方面,高濃度的硼滲雜,可以藉它在矽晶內的晶格間引起的應力而消除業經生成的氧化誘導堆積缺陷。但是,如果硼滲雜的表面濃度過?,高於10^20cm^-3 ,則該等應力有可能促成滑線斷層(Slip Line Dislocation)的?生。滑線斷層的發生可以使PN接面二極體?生嚴重的反向漏電流。
- 英文摘要: An investigation of the electrically active defect presented on silicon epitaxial layer deposited by the hydrogen reduction of silicon tetrachloride (SiCl4) at 1050°C has been made. The silicon substrate was treated in a significant amount of high temperature and critical processing prior to the deposition of epitaxial layer. Epitaxial stacking faults (SFepi) and hillocks are delineated on the epitaxial silicon by Wright preferential etch. By means of anodic etching technique, both SFepi and hillock defect are demonstrated to be electrically active, with the former one more active than the latter one. If the epi wafer is oxidized in high temperature steam atmosphere before etching, then some of the hillocks will transform into surface-type oxidation induced stacking fault (SFs). The As ion-implanted buried layer demonstrates gettering effect of denuding the formation of stacking fault during the epitaxial deposition. On the other hand, the oxidation induced stacking fault can be annihilated by solute lattice contraction stress introduced by high concentration boron diffusion. However, if the heavily boron doped silicon surface concentration exceeds about 1020 cm-3, the stress will likely cause slip line dislocation. Slip line dislocation has been observed to constitute serious leakage problem in pn junction diode.
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