• 作者： 張慶元; 林俞伸
• 作者服務機構： 清華大學電機工程研究所
• 中文摘要： 應用餘時技術RESO（REcomputation with Shifted Operand）和AL（Alternative Logic）在二個呆滯的時序中，以重複計算來設計心脈式容錯乘法器。利用工作時序的計算結果，及兩個呆滯時序中重複計算即形成三倍餘份架構。在Sun 3工作站上，一個3x3容錯帶形乘法器被完成及模擬於VALID工具。對每個乘法細胞元，外加的面積及時間分別約為(9.8n+5)/(n2+4n)+0.05及18/(6n+7)，其中n為位元。當n增大時，二者皆減少。
• 英文摘要： A fault-tolerant array multiplier design with 33% utilization is proposed by applying time redundancytechniques named RESO (REcomputation with Shifted Operand) and AL (Alternative Logic) to the twoidle phases．Thus, triple modular redundancy (TMR) can be formed by employing the three results ofnormal computation and two recomputations obtained in two idling phases. If one of the computationsis incorrect due to a transient fault, the output is still valid because the two remaining fault-free resultsmask the faulty one when the majority voter is performed. However, if the transient fault occurs in thenormal computation phase, the multiplication process thus experiences two phase delays in recovery. Onthe other hand, if the transient fault occurs in the recomputation cycles, the multiplication process is notaffected. Permanent faults in the proposed scheme can, be detected, and faulty cells can be located. The area overhead and time overhead for each multiplier are approximately (9.8n+5)/(n2+4n)+0.05and 18/(6n+7), respectively, where n is the number of bits Both overheads are reduced when n increases.To verify the correctness of the proposed scheme, concurrent fault-tolerant 3x3 band matrix multiplicationwith a 4-bitx4-bit multiplier in each systolic cell was implemented and simulated successfully by the VALIDtool on a Sun 3 workstation.
• 中文關鍵字： fault-tolerance; systolic; time redundancy; transrent/permanent fault; TMR
• 英文關鍵字： --