- 作者: JEN-SHIUN CHIANG ; JUN-YAO LIAO
- 中文摘要: Due to advances in very large scale integrated circuit (VLSI) technology, the chip area of integrated circuits (IC) has increased significantly. However, power efficiency and performance have not proportionally improved. The main reason is the very high capacitive load of the global clock. On the other hand, the asynchronous circuit needs no global clock and it can overcome the difficulties that are met in synchronous circuit design. This paper describes a technique for asynchronous circuit design which uses a new asynchronous control unit that is composed of pass transistors. This asynchronous control unit has the advantages of simplicity and ease of implementation. We used the Taiwan Semiconductor Manufacturing Company (TSMC) 0.6 mm single-poly double-metal process to design and implement an 8-b?-b pipelined multiplier associated with an asynchronous control unit. HSPICE simulation results show that the feed through rate of the inputs can be as high as 250 MHz.
- 英文摘要: --
- 中文關鍵字: asynchronous circuit, Booth decoder, bounded delay model, clock skew, delay insensitive, micropipiline, Muller C-element, pass transistor, pipelined multiplier, quasi delay insensitive
- 英文關鍵字: --