- 作者: 賴飛罷; 洪春敬; 龐臺銘
- 作者服務機構: 國立台灣大學電機及資訊工程研究所
- 中文摘要: 精減指令集電腦系統遇到跳躍或分支指令時,將使系統執行管線出現空洞(bubble),為降低此效應,我們提出一個零延遲跳躍能力的新架構,零延遲跳躍架構包含五個處理單元:指令擷取單元(IFU),整數處理單元(IPU),浮點處理單元(FPU),串列處理單元(LPU),和記憶體管理單元與快記憶體控制器(MMU/CC)。在此架構中,複雜暫存器存取和算術邏輯單元運算之臨界路徑,被分散到整數處理單元及串列處理單元,串列處理單元提供零延遲串列存取,指令擷取單元提供零延遲分支和超零跳躍(super-zero-delay),內部前饋機制和強行擠入(squashing)運算將在本文中討論。
- 英文摘要: The zero-delay branch architecture MARS contains five processing units: the IFU (Instruction FetchUnit), the IPU (Integer Processing Unit), the FPU (Floating Point Unit), the LPU (List Processing Unit),and the MMU/CC (Memory Management Unit/Cache Controller). In this architecture, the critical path ofthe complex register file access and the ALU operation are distributed to the LPU and the IPU, and thetracing of the list can be done quickly by the non-delay car and cdr instructions of the LPU. By using onenew branch control mechanism (called the branch peephole), ARS can achieve zero delay branch andsuper-zero-jump. Special circuits for the internal forwarding mechanism and squashing operation areimplemented.
- 中文關鍵字: zero-delay; branch; super-zero-jump; internal forwarding; squashing; list access; type checking; shallow blinding; pipe;ine stage; branch peephole; garbage collection
- 英文關鍵字: --