- 作者: 李舉賢
- 作者服務機構: 國立台灣大學
- 中文摘要:
將筆者曾於1972年研成之電晶體延遲電路(參見年終報告附錄),應用於裝配一8位
以上之字碼產生器,該產生器系統係以一?正反器及另一?電晶體延遲電路構成而得,其
研究步賺與方法如下:
(1)就用兩箇4001型電晶體所構或之正反器電路,先作靜態分析之後,再以實驗對於正
反器之動態操作加以研究。導致平衡電阻(Equalizing resistor),該電阻可改進正反
器之轉換特性,並對此加以分析與檢討。
(2)按照最重負載(最小輸出電阻),R1min,及平衡電阻,Re,之理論分析所得結果
,設計一連結電路(Coupling network),以匹配正反器及延遲電路而得一聯合電路系
統,並使其做正確的操作。
(3)使用上項所得之聯電合路8箇,連續串聯,以裝配一8位移位記錄器(Shift reg-
rster),並用實驗研究其移位特性。經稍修改外部接線之後,得一8位,時間性字碼產
生器(Temporal word generator);該器所能供出字碼之最高頻率為250KHZ o
上面研究之詳細內容,分別論述於筆者六十二年度年終報告及其附錄中。
r - 英文摘要: 399PROCEEDINS OF THENATIONAL SCIENCE COUNCILNumber 8 Part 3, May 1975TRANSISTOR DELAY CIRCUITS APPLIED INBUILDING A WORD GENERATORChu-Hsien LeeDepartment of Electrical Engineering, National Taiwan UniversityABSTRACT The storage transistor delay circuit4, which was developed by thewriter in 1972, is to be applied in implementing a word generator which canproduce a temporal (or serial) binary code of 6 bits or more. The systemto be implemeted consists of a family of identical flip-flops (or binaries)and a family of identical transistor delay circuits, which is wired so thateach binary is followed by a delay circuit and that is in turn followed bya succeeding binary. In this study, discrete junction transistors of typeCE4001 are used both for the delay circuits and the flip-flops. The designconsiderations for the flip-flops and the coupling networks between thedelay circuit and the flip-fiop are described. The oberation performance isstudied experimentally for a model of 6-bit word generator, and the resultshows that the system operates satisfactorily in sending out a temporalcode of a repetition frequency below 250 KHz (corresponding to a pulseinterval of 4 microsecond).I. A SUMMARY ACCOUNT OF STORAGE TRANSISTOR DELAY CIRCUITThe basis of operation and the design rules were reported by the writer in "StorageTransistor Delay Circuit", Proc. IEEE, Vol, 60, No.4, April; 1972, pp. 466-467. Asthis type of the delay circuits is to be used in this study, a brief description forthe circuit performance will be given here.Fig.1 illustrates the basic storage transistor delay circuit, and Fig.2 shows a set ofFig. 1.The storage transistor-delay circuit.
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