• 作者： 盧志遠
• 作者服務機構： 國立交通大學電子研究所
• 中文摘要： 由於高密度的要求，超大型積體電路中的複矽晶電阻器需要縮小其體積。本研究報導複矽晶電阻器的長度及其厚度縮小時的實驗現象。同時也將提出理論模型來解釋所觀察到的事實。 當複矽晶膜之厚度由1.2微米縮小到o.1微米，電阻係數並非常數，而是以指數之方式變大。此現象主要是由於晶粒體積之縮小與導電載子被陷井捕捉所致，而非如某些學者所建議的表面碰撞效應所致。當電阻器在一定的偏壓之下縮短，其電流－電壓特性曲線將會有非線性的現象。吾人在此非線性區中觀察到某些怪異的現象，這些現象無法用現存的單一晶粒體積模型解釋。吾人提出非單一晶粒體積模型來描述以上所觀察到的怪異現象。綜言之，吾人詳細地觀察了複矽晶電阻器的縮尺效應，並提出適當的模型予以解釋。
• 英文摘要： The applications of polysilicon resistors in VLSI circuits demand small device dimensions. This workreports new experimental observations when the polysilicon resistor length and film thickness decrease, andintroduces a theoretical model to explain these observations. When the polysilicon film thickness decreases from 1.2 um down to 0.1 μm, the resistivity is notconstant but increases exponentially. This is primarily due to the carrier trapping and grain-size reductionrather than of the surface scattering as recently suggested by some other workers. As the resistor lengthdecreases at a constant bias, the I-V characteristics becomes non-linear. Some anomalous behaviors in thisnon-linear regime, which can not be understood by using previous uniform grain-size models, are observedand described by a new non-uniform grain-size conduction model. From these observations, the scalingeffects on electrical properties of polysilicon resistor are thoroughly investigated, and are properly explain-ed by the new theoretical model.
• 中文關鍵字： polysilicon; VLSI; resistor; scalling effects
• 英文關鍵字： --